SETINTA=NO_EFFECT, SRCINC=NO_INCREMENT, DSTINC=NO_INCREMENT, RELOAD=DISABLED, SETINTB=NO_EFFECT, CLRTRIG=NOT_CLEARED, WIDTH=8_BIT, SWTRIG=NOT_SET, CFGVALID=NOT_VALID
Transfer configuration register for DMA channel 0.
| CFGVALID | Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 (NOT_VALID): Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 1 (VALID): Valid. The current channel descriptor is considered valid. |
| RELOAD | Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 0 (DISABLED): Disabled. Do not reload the channels’ control structure when the current descriptor is exhausted. 1 (ENABLED): Enabled. Reload the channels’ control structure when the current descriptor is exhausted. |
| SWTRIG | Software Trigger. 0 (NOT_SET): Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 1 (SET): Set, When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. |
| CLRTRIG | Clear Trigger. 0 (NOT_CLEARED): Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 1 (CLEARED): Cleared. The trigger is cleared when this descriptor is exhausted. |
| SETINTA | Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 0 (NO_EFFECT): No effect. 1 (SET): Set. The INTA flag for this channel will be set when the current descriptor is exhausted. |
| SETINTB | Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 0 (NO_EFFECT): No effect. 1 (SET): Set. The INTB flag for this channel will be set when the current descriptor is exhausted. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| WIDTH | Transfer width used for this DMA channel. 0 (8_BIT): 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 1 (16_BIT): 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 2 (32_BIT): 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 3 (RESERVED): Reserved. Reserved setting, do not use. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| SRCINC | Determines whether the source address is incremented for each DMA transfer. 0 (NO_INCREMENT): No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 1 (1_X_WIDTH): 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 2 (2_X_WIDTH): 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 3 (4_X_WIDTH): 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. |
| DSTINC | Determines whether the destination address is incremented for each DMA transfer. 0 (NO_INCREMENT): No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 1 (1_X_WIDTH): 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 2 (2_X_WIDTH): 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 3 (4_X_WIDTH): 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. |
| XFERCOUNT | Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. … 0x3FF = a total of 1,024 transfers will be performed. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |